Invention Grant
- Patent Title: Store buffer supporting direct stores to a coherence point
-
Application No.: US15621759Application Date: 2017-06-13
-
Publication No.: US10282298B2Publication Date: 2019-05-07
- Inventor: Patrick P. Lai
- Applicant: Microsoft Technology Licensing, LLC
- Applicant Address: US WA Redmond
- Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
- Current Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
- Current Assignee Address: US WA Redmond
- Agency: Alleman Hall Creasman & Tuttle LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0831 ; G06F12/0811 ; G06F12/0815

Abstract:
A system that uses a write-invalidate protocol has two types of stores: a traditional store that operates using a write-back policy that snoops for copies of the cache line at lower cache levels, and a store that writes, using a coherent write-through policy, directly to the last-level cache without snooping the lower cache levels. A separate store buffer may be maintained in the processor for the coherent write-through operations. A special bit may be maintained in the entries of a store buffer that is used for both traditional write-back policy stores and for coherent write-through policy. This bit indicates that loads and stores older than the last speculative store in the store buffer are allowed to be performed.
Public/Granted literature
- US20180357172A1 STORE BUFFER SUPPORTING DIRECT STORES TO A COHERENCE POINT Public/Granted day:2018-12-13
Information query