According to one embodiment, a semiconductor integrated circuit includes a bus master, a bus slave and a clock gating circuit. The bus master outputs an access request. The bus slave transmits a response to the access request to the bus master. The clock gating circuit shuts off clocks supplied to the bus slave. The bus slave includes a control circuit which outputs first and second signals in response to the access request; a first circuit which outputs a third signal in response to a clock supplied from the clock gating circuit, when the first signal is asserted; and a second circuit which receives the third signal output from the first circuit and the second signal, and outputs a fourth signal as the response to the bus master, when the second signal is asserted.