Invention Grant
- Patent Title: Three-stage memory arrangement
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Application No.: US13813767Application Date: 2011-07-22
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Publication No.: US10282320B2Publication Date: 2019-05-07
- Inventor: Joern Schriefer , Juergen Scherschmidt , Thomas Peichl
- Applicant: Joern Schriefer , Juergen Scherschmidt , Thomas Peichl
- Applicant Address: DE Frankfurt
- Assignee: CONTINENTAL TEVES AG & CO. OHG
- Current Assignee: CONTINENTAL TEVES AG & CO. OHG
- Current Assignee Address: DE Frankfurt
- Agency: Brinks Gilson & Lione
- Priority: DE102010038850 20100803
- International Application: PCT/EP2011/062680 WO 20110722
- International Announcement: WO2012/016866 WO 20120209
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G05B19/042

Abstract:
An electronic memory arrangement having at least three memory areas, a memory control unit, and a writing memory-accessing unit configured to carry out write access. A reading memory-accessing unit is configured to carry out read accesses. The memory control unit determines read and write access to the at least three memory areas, and the memory control unit is configured such that after the writing of a first data packet to one of the three memory areas, a following second data packet to be written is written to one on the three memory area to which read access does not place simultaneously during the write access of the second data packet.
Public/Granted literature
- US20130132697A1 THREE-STAGE MEMORY ARRANGEMENT Public/Granted day:2013-05-23
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