Invention Grant
- Patent Title: Mitigating length-of-diffusion effect for logic cells and placement thereof
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Application No.: US15193003Application Date: 2016-06-25
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Publication No.: US10282503B2Publication Date: 2019-05-07
- Inventor: Benjamin John Bowers , Anthony Correale, Jr. , Tracey Della Rova
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C./Qualcomm
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L27/02 ; H01L27/092

Abstract:
Systems and methods relate to cell placement methodologies for improving length of diffusion of transistors. For example, a first transistor with a first diffusion node which is bounded by a first diffusion cut is identified in a transistor level layout. The first diffusion cut is replaced with a first floating gate, and a first filler cell with a first filler diffusion region is added to extend a length of diffusion of the first diffusion node. Increasing the length of diffusion leads to improving drive strength and performance of the first transistor.
Public/Granted literature
- US20170371994A1 MITIGATING LENGTH-OF-DIFFUSION EFFECT FOR LOGIC CELLS AND PLACEMENT THEREOF Public/Granted day:2017-12-28
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