- Patent Title: Simultaneous latency and rate coding for automatic error correction
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Application No.: US14279375Application Date: 2014-05-16
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Publication No.: US10282660B2Publication Date: 2019-05-07
- Inventor: Victor Hokkiu Chan , Ryan Michael Carey
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Patterson & Sheridan, LLP
- Main IPC: G06N7/02
- IPC: G06N7/02 ; G06N7/04 ; G06N7/06 ; G06N7/08 ; G06N3/08 ; G06N3/04

Abstract:
Methods and apparatus are provided for identifying environmental stimuli in an artificial nervous system using both spiking onset and spike counting. One example method of operating an artificial nervous system generally includes receiving a stimulus; generating, at an artificial neuron, a spike train of two or more spikes based at least in part on the stimulus; identifying the stimulus based at least in part on an onset of the spike train; and checking the identified stimulus based at least in part on a rate of the spikes in the spike train. In this manner, certain aspects of the present disclosure may respond with short response latencies and may also maintain accuracy by allowing for error correction.
Public/Granted literature
- US20150193680A1 SIMULTANEOUS LATENCY AND RATE CODING FOR AUTOMATIC ERROR CORRECTION Public/Granted day:2015-07-09
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