Invention Grant
- Patent Title: Semiconductor memory device having a semiconductor chip including a memory cell and a resistance element
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Application No.: US15699847Application Date: 2017-09-08
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Publication No.: US10283201B2Publication Date: 2019-05-07
- Inventor: Satoshi Inoue , Daisuke Arizono
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Priority: JP2017-060033 20170324
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C7/10 ; G11C11/00 ; G11C7/04

Abstract:
According to one embodiment, a semiconductor device includes: a first memory cell provided in a first semiconductor chip; a first output buffer circuit configured to output data of the first memory cell outside, the first output buffer circuit provided in the first semiconductor chip; a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit, a first terminal connected to the first calibration control circuit, the first calibration control circuit provided in the first semiconductor chip; and a first resistance element connected to the first terminal, the first resistance element provided in the first semiconductor chip.
Public/Granted literature
- US20180277216A1 SEMICONDUCTOR DEVICE Public/Granted day:2018-09-27
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