Invention Grant
- Patent Title: Method of integrating capacitors on lead frame in semiconductor devices
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Application No.: US15282619Application Date: 2016-09-30
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Publication No.: US10283441B2Publication Date: 2019-05-07
- Inventor: Fulvio Vittorio Fontana , Giovanni Graziosi
- Applicant: STMICROELECTRONICS S.R.L.
- Applicant Address: IT Agrate Brianza
- Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee: STMICROELECTRONICS S.R.L.
- Current Assignee Address: IT Agrate Brianza
- Agency: Seed IP Law Group LLP
- Priority: IT102016000020111 20160226
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L49/02

Abstract:
In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.
Public/Granted literature
- US20170250128A1 METHOD OF INTEGRATING CAPACITORS IN SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE Public/Granted day:2017-08-31
Information query
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