- Patent Title: Three dimensional semiconductor memory device in which a channel layer has a stacked structure including an outer semiconductor layer and a doped inner semiconductor layer
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Application No.: US15696372Application Date: 2017-09-06
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Publication No.: US10283522B2Publication Date: 2019-05-07
- Inventor: Tomofumi Zushi , Shinya Naito
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2017-054765 20170321
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L29/10 ; H01L29/06 ; H01L21/28 ; H01L27/11565

Abstract:
According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. The channel layer has a stacked structure that includes an outer channel semiconductor layer, an intermediate layer made of an insulating material, and an inner channel semiconductor layer, from a side of the memory film. Both of the outer channel semiconductor layer and the inner channel semiconductor layer are electrically connected to the semiconductor layer.
Public/Granted literature
- US20180277560A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2018-09-27
Information query
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