Invention Grant
- Patent Title: High gain load circuit for a differential pair using depletion mode transistors
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Application No.: US14959567Application Date: 2015-12-04
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Publication No.: US10284194B2Publication Date: 2019-05-07
- Inventor: Yogesh Jayaraman Sharma , James Fiorenza
- Applicant: Analog Devices, Inc.
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H03K5/22
- IPC: H03K5/22 ; H03K17/687 ; H01L27/088 ; H01L29/20 ; H03F3/45

Abstract:
A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.
Public/Granted literature
- US20160164517A1 High Gain Load Circuit for a Differential Pair Using Depletion Mode Transistors Public/Granted day:2016-06-09
Information query
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