- Patent Title: System and method for bit processing in a central network component
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Application No.: US13913971Application Date: 2013-06-10
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Publication No.: US10284247B2Publication Date: 2019-05-07
- Inventor: Abhijit Kumar Deb , Hubertus Gerardus Hendrikus Vermeulen , Sujan Pandey
- Applicant: NXP B.V.
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Agent Rajeev Madnawat
- Main IPC: H04B1/38
- IPC: H04B1/38 ; H04B1/3822 ; H04L12/40

Abstract:
A central network component, a FlexRay-compatible central network component, and a method for bit processing in a central network component are described. In one embodiment, a central network component for facilitating communication among communication nodes includes a bit oversampling module configured to oversample bits received from a first communication node of the communication nodes with an oversampling factor to generate oversampled bit streams, a time point selection module configured to select time points in the oversampled bit streams, where the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor, and a bit outputting module configured to output the inner samples to a second communication node of the communication nodes between the time points. Other embodiments are also described.
Public/Granted literature
- US20140362893A1 SYSTEM AND METHOD FOR BIT PROCESSING IN A CENTRAL NETWORK COMPONENT Public/Granted day:2014-12-11
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