A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. Each hard drive sub-board is coupled to one or more expanders, via and interface unit, with a set of dual-pass shielded cables. The expander includes a plurality of chipsets coupled to a complex logic device. Each chipset may communicate with a different subset of hard drives with potentially different timing characteristics. The dual-pass shielded cables may be arranged to mitigate these differences. In addition, pin assignments associated with the cables may be set in order to further mitigate the timing differences.