A data processing apparatus 10 for executing an access instruction for n threads in order to access data values for the n threads includes storage circuitry 100 that stores data values associated with the n threads in groups defined by storage boundaries. The data processing apparatus also includes processing circuitry 80 that processes the access instruction for a set of threads at a time (where each set of threads comprises fewer than n threads) and splitting circuitry 110, responsive to the access instruction, to divide the n threads into multiple sets of threads, and to generate at least one control signal identifying the multiple sets. For each of the sets, the processing circuitry responds to the at least one control signal by issuing at least one access request to the storage circuitry in order to access the data values for that set. The splitting circuitry determines into which set each of the n threads is allocated having regards to the storage boundaries.