Invention Grant
- Patent Title: Multi-processor with selectively interconnected memory units
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Application No.: US15811192Application Date: 2017-11-13
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Publication No.: US10296488B2Publication Date: 2019-05-21
- Inventor: Martin Vorbach
- Applicant: SCIENTIA SOL MENTIS AG
- Applicant Address: CH Schindellegi
- Assignee: PACT XPP SCHWEIZ AG
- Current Assignee: PACT XPP SCHWEIZ AG
- Current Assignee Address: CH Schindellegi
- Agent Aaron Grunberger
- Priority: DE10241812 20020906; DE10315295 20030404; DE10321834 20030515; EP03019428 20030828
- Main IPC: H03K19/173
- IPC: H03K19/173 ; G06F15/78 ; G06F13/16 ; G06F9/30 ; G06F13/36 ; G06F13/40
Abstract:
A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units.
Public/Granted literature
- US20180067896A1 MULTI-PROCESSOR WITH SELECTIVELY INTERCONNECTED MEMORY UNITS Public/Granted day:2018-03-08
Information query
IPC分类:
