Invention Grant
- Patent Title: Optimizing designs of integrated circuits
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Application No.: US14963219Application Date: 2015-12-08
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Publication No.: US10296690B2Publication Date: 2019-05-21
- Inventor: Jovanka Ciric Vujkovic , Kenneth S. McElvain
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: HIPLegal LLP
- Agent Judith Szepesi
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods and systems for optimizing and/or designing integrated circuits. In one embodiment, a method for dynamically routing a net from equivalent resources is described, comprising identifying a critical load, determining whether a driver driving the critical load drives other components, and whether the critical load requires an improvement in slack, replicating the driver, to create a replicated driver, when the critical load requires an improvement in slack, coupling the replicated driver to the load; and tagging the replicated driver.
Public/Granted literature
- US20160092609A1 Optimizing Designs of Integrated Circuits Public/Granted day:2016-03-31
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