A memory stores layout data of a semiconductor circuit. A processor searches for a plurality of wiring routes on the basis of a plurality of cost calculating formulas that respectively represent a plurality of design rules, and on the basis of the layout data, wherein the plurality of wiring routes are a plurality of candidates for a wiring route that corresponds to a processing target net that is connection information that needs to be changed in the semiconductor circuit, and respectively satisfy the plurality of design rules. Then, the processor generates display information that displays the plurality of wiring routes obtained by the search.