- Patent Title: System and method for visualization in an electronic circuit design
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Application No.: US15709948Application Date: 2017-09-20
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Publication No.: US10296703B1Publication Date: 2019-05-21
- Inventor: Pardeep Juneja , Jean-Marc Bourguet , Joyjeet Bose , Sachin Shrivastava , Yashu Gupta , Ankur Chaplot
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Holland & Knight LLP
- Agent Mark H. Whittenberger, Esq.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The present disclosure relates to a system and method for visualization of fixing of design rule violations in an electronic circuit design. Embodiments may include displaying at a graphical user interface at least a portion of an electronic design having at least one shape associated therewith and identifying one or more electronic design rules associated with the at least one shape. In response to identifying, embodiments may include determining a proposed shape based upon, at least in part, the one or more electronic design rules associated with the at least one shape, wherein the proposed shape is at least one of a trim shape, a bridge shape, and a patch shape and displaying the proposed shape at the graphical user interface.
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