Invention Grant
- Patent Title: Reduced power implementation of computer instructions
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Application No.: US14583300Application Date: 2014-12-26
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Publication No.: US10297001B2Publication Date: 2019-05-21
- Inventor: Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
- Applicant: Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- Main IPC: G06T1/20
- IPC: G06T1/20 ; G09G5/00 ; G06T15/80 ; G09G5/36 ; G06F7/00 ; G06F9/30

Abstract:
Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.
Public/Granted literature
- US20160189327A1 REDUCED POWER IMPLEMENTATION OF COMPUTER INSTRUCTIONS Public/Granted day:2016-06-30
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