A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. The semiconductor apparatus may include an input/output control latch circuit configured to output the internal address as a first latch address based on the second decoding command and the delayed decoding command. The semiconductor apparatus may include an input control latch circuit configured to output the internal address as a second latch address based on the first decoding command.