Invention Grant
- Patent Title: Switched interface stacked-die memory architecture
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Application No.: US16026833Application Date: 2018-07-03
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Publication No.: US10297340B2Publication Date: 2019-05-21
- Inventor: Joe M. Jeddeloh , Paul A. LaBerge
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F13/42 ; G11C5/02 ; G06F13/16 ; G11C29/04 ; G11C7/10 ; G11C8/10

Abstract:
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request directly to an address decoder associated with a stacked-die memory vault without knowing whether a repair address is required. If a subsequent analysis of the memory request shows that a repair address is required, an in-process decode of the requested memory address can be halted and decoding of the repair address initiated.
Public/Granted literature
- US20180358111A1 SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE Public/Granted day:2018-12-13
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