Invention Grant
- Patent Title: Trench isolation interfaces
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Application No.: US15641478Application Date: 2017-07-05
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Publication No.: US10297493B2Publication Date: 2019-05-21
- Inventor: Arup Bhattacharyya
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L21/765 ; H01L21/763 ; H01L21/762 ; H01L27/11548 ; H01L27/11575

Abstract:
The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. An material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.
Public/Granted literature
- US20190013234A1 TRENCH ISOLATION INTERFACES Public/Granted day:2019-01-10
Information query
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