Invention Grant
- Patent Title: Stacked vertical NFET and PFET
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Application No.: US15858267Application Date: 2017-12-29
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Publication No.: US10297513B1Publication Date: 2019-05-21
- Inventor: Tenko Yamashita , Chen Zhang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Vazken Alexanian; Michael J. Chang, LLC
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/822 ; H01L29/10 ; H01L29/08 ; H01L29/06 ; H01L21/84 ; H01L29/66 ; H01L21/02 ; H01L21/768 ; H01L29/51 ; H01L29/49 ; H01L21/28 ; H01L29/78 ; H01L27/092 ; H01L27/12 ; H01L21/225 ; H01L27/06
Abstract:
The present invention provides stacked VFET devices. In one aspect, a method of forming a stacked VFET device includes: patterning a fin(s) in a wafer having a vertical fin channel of a VFET1 separated from a vertical fin channel of a VFET2 by an insulator; forming a bottom source and drain of the VFET1 below the vertical fin channel of the VFET1; forming a gate of the VFET1 alongside the vertical fin channel of the VFET1; forming a gate of the VFET2 alongside the vertical fin channel of the VFET2; forming a top source and drain of the VFET1 above the vertical fin channel of the VFET1; forming a bottom source and drain of the VFET2 below the vertical fin channel of the VFET2; and forming a top source and drain of the VFET2 above the vertical fin channel of the VFET2. A stacked VFET device is also provided.
Information query
IPC分类:
