Invention Grant
- Patent Title: Land side and die side cavities to reduce package z-height
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Application No.: US15664735Application Date: 2017-07-31
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Publication No.: US10297542B2Publication Date: 2019-05-21
- Inventor: MD Altaf Hossain , Scott A. Gilbert
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/00 ; H01L21/48 ; H01L23/498 ; H01L23/13 ; H01L25/16 ; H05K1/11 ; H01L23/64 ; H01L21/768 ; H01L49/02 ; H01L23/538 ; H01L25/065 ; H05K1/18 ; H04M1/02

Abstract:
A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
Public/Granted literature
- US20180108605A1 LAND SIDE AND DIE SIDE CAVITIES TO REDUCE PACKAGE Z-HEIGHT Public/Granted day:2018-04-19
Information query
IPC分类: