Invention Grant
- Patent Title: Trimming method, trimming circuity, and trimming system for integrated circuit with memory usage reduction
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Application No.: US15839813Application Date: 2017-12-12
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Publication No.: US10297558B1Publication Date: 2019-05-21
- Inventor: Tzong-Honge Shieh , Po-Hsiang Fang
- Applicant: Novatek Microelectronics Corp.
- Applicant Address: TW Hsinchu
- Assignee: Novatek Microelectronics Corp.
- Current Assignee: Novatek Microelectronics Corp.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/00 ; G11C16/08 ; G01P21/00 ; G11C5/00 ; H03L7/00 ; G11C16/06 ; H01L35/00 ; H01L23/58 ; H01L21/66 ; H01L23/525 ; G11C17/16

Abstract:
The disclosure provides a trimming method, a trimming circuitry, and a trimming system for an IC with memory usage reduction. The method is applicable to a system including a tester, a characteristic adjustable circuit, and a trimming circuitry having a characteristic outputting circuit, a data memory, and a trim memory. The method includes the following steps. Under each condition, output signals respectively corresponding to trim settings are received from the characteristic adjustable circuit by the characteristic outputting circuit to obtain output values of the condition, a statistical parameter associated with the output values of the condition is calculated by the tester. The statistical parameter of at least one of the conditions is written into the data memory by the tester. An optimal trim setting of the characteristic adjustable circuit is determined according to the statistical parameters under all the conditions and written into the trim memory by the tester.
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