In a method for manufacturing a transistor, a gate structure may be formed on a semiconductor substrate. A first material layer may be formed on the gate structure to expose an upper sidewall of the gate structure. A spacer including a second material layer may be formed on the upper sidewall of the gate structure. The first material layer may be isotropically etched using the spacer as an etch mask to form a space. An insulating interlayer may be formed on the semiconductor substrate. The insulating interlayer may not be formed in the space.