Invention Grant
- Patent Title: Method of manufacturing a semiconductor device having two types of gate electrodes
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Application No.: US15868120Application Date: 2018-01-11
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Publication No.: US10297683B2Publication Date: 2019-05-21
- Inventor: Yusuke Kobayashi , Yuichi Onozawa , Manabu Takei , Akio Nakagawa
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: Rabin & Berdo, P.C.
- Priority: JP2014-167427 20140820
- Main IPC: H01L29/739
- IPC: H01L29/739 ; H01L29/78 ; H01L29/06 ; H01L29/10 ; H01L29/423 ; H01L29/66 ; H01L29/40

Abstract:
In mesa regions between adjacent trenches disposed in an n−-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.
Public/Granted literature
- US20180158939A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Public/Granted day:2018-06-07
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