Invention Grant
- Patent Title: Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains
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Application No.: US15470880Application Date: 2017-03-27
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Publication No.: US10310013B2Publication Date: 2019-06-04
- Inventor: Guangyuan Kelvin Ge , Rajesh Kashyap
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR
- Agency: Renaissance IP Law Group LLP
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/317 ; G01R31/3185

Abstract:
Embodiments include a power isolation circuit. The power isolation circuit includes a logic block, a wrapper cell, an isolation cell, a test control unit, and/or a power control unit. The power control unit is coupled to the isolation cell and configured to receive a DFT internal core test mode control signal and a clamp control signal, and control the isolation cell dependent on the DFT internal core test mode control signal and the clamp control signal. Also disclosed is a multi-power domain multi-power isolation system, which includes a first power domain and a second power domain. The first power domain includes a logic block, wrapper cells, isolation cells, and a power control unit. The second power domain includes a logic block, wrapper cells, and level-shifter cells. The power control unit is coupled to the isolation cells. Additional power domains with similar characteristics can be included in the design.
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