Invention Grant
- Patent Title: Level of detail selection during ray tracing
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Application No.: US15004191Application Date: 2016-01-22
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Publication No.: US10311629B2Publication Date: 2019-06-04
- Inventor: David Baldwin , Karthik Vaidyanathan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop Pruner & Hu, P.C.
- Main IPC: G06T15/00
- IPC: G06T15/00 ; G06T15/06

Abstract:
A level of detail node may hold in a bounding volume hierarchy, an object identifier, a distance at which a transition occurs between levels of detail and a bias. When a level of detail node is encountered in the hierarchy, the distance value may be used to select a level of detail. Sometimes a different level of detail is loaded because the preferred level is not available. The different level may be marked in a register. Then for a subsequence frame, the correct level is used. A node bias may be used to override the level of detail selection is some cases.
Public/Granted literature
- US20170213379A1 Level of Detail Selection During Ray Tracing Public/Granted day:2017-07-27
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |