The purpose of the present invention is to suppress the fluctuation of a data line voltage that occurs when an analog voltage signal is sampled and held in a data line in a display device provided with a current-driven display element. Transistors (SWr, SWG, SWb) of each demultiplexer (252) are successively switched on, for each predetermined period, in a selection period of a write control line (SW_LR(i)). In a period when the transistor (SWr) is switched on, an analog video signal (Dj) from a data voltage output unit circuit (211d) is applied to a data line (SLrj) and a pixel circuit (50r). When the transistor SWr is then switched off, the voltage held by the data line (SLrj) decreases below the voltage of the analog video signal (Dj) due to a parasitic capacitance (Cssdr). However, the voltage of a voltage fluctuation compensation line (G3_Cnt (i)) changes from a low level to a high level within the selection period. This causes the voltage of the data line (SLrj) to rise via a capacitor (Ccnt), and the decrease in voltage to be compensated for.