Invention Grant
- Patent Title: High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
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Application No.: US14835093Application Date: 2015-08-25
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Publication No.: US10312134B2Publication Date: 2019-06-04
- Inventor: Qingmin Liu
- Applicant: SunEdison Semiconductor Limited (UEN201334164H)
- Applicant Address: TW Hsinchu
- Assignee: GlobalWafers Co., Ltd.
- Current Assignee: GlobalWafers Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Armstrong Teasdale LLP
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L31/0256 ; H01L21/762 ; H01L21/02 ; H01L21/324 ; H01L27/12 ; H01L29/06
Abstract:
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.
Public/Granted literature
- US20160071760A1 HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS Public/Granted day:2016-03-10
Information query
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