Invention Grant
- Patent Title: Method and structure for forming MOSFET with reduced parasitic capacitance
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Application No.: US15856309Application Date: 2017-12-28
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Publication No.: US10312148B2Publication Date: 2019-06-04
- Inventor: Kangguo Cheng , Peng Xu , Chen Zhang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: McGinn IP Law Group, PLLC
- Agent Vazken Alexanian
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/51 ; H01L29/78 ; H01L29/66 ; H01L23/532 ; H01L23/482 ; H01L29/417

Abstract:
A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.
Public/Granted literature
- US20180122915A1 METHOD AND STRUCTURE FOR FORMING MOSFET WITH REDUCED PARASITIC CAPACITANCE Public/Granted day:2018-05-03
Information query
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