Invention Grant
- Patent Title: Monolithic co-integration of MOSFET and JFET for neuromorphic/cognitive circuit applications
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Application No.: US15818674Application Date: 2017-11-20
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Publication No.: US10312151B1Publication Date: 2019-06-04
- Inventor: Karthik Balakrishnan , Bahman Hekmatshoartabari , Alexander Reznicek , Jeng-Bang Yau
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Hoffmann & Baron, LLP
- Agent L. Jeffrey Kelly, Esq.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8234 ; H01L27/085 ; H01L29/808 ; H01L29/66
Abstract:
Vertical MOSFET and JFET devices are incorporated on the same chip, enabling circuit designs that benefit from the simultaneous use of such devices. A fabrication method allows formation of the devices using a shared source/drain layer on a bulk semiconductor substrate.
Public/Granted literature
- US20190157161A1 MONOLITHIC CO-INTEGRATION OF MOSFET AND JFET FOR NEUROMORPHIC/COGNITIVE CIRCUIT APPLICATIONS Public/Granted day:2019-05-23
Information query
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