Invention Grant
- Patent Title: ESD protection circuit having clamp control loop
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Application No.: US15015492Application Date: 2016-02-04
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Publication No.: US10312230B2Publication Date: 2019-06-04
- Inventor: Cynthia A. Torres
- Applicant: FREESCALE SEMICONDUCTOR, INC.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Agent Mary Jo Bertani
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H02H9/04

Abstract:
Electrostatic discharge (ESD) protection circuitry in an integrated circuit is provided. The protection circuitry includes a trigger circuit coupled between a first power supply bus and a second power supply bus. A delay circuit is coupled to receive an output signal from the trigger circuit. The delay circuit includes a first inverter coupled to the input of the delay circuit and a feedback transistor having a control terminal coupled to the output of the delay circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the output of the first inverter. A clamp driver circuit is coupled to the output of the delay circuit.
Public/Granted literature
- US20170229444A1 ESD PROTECTION CIRCUIT Public/Granted day:2017-08-10
Information query
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