Invention Grant
- Patent Title: Semiconductor device and method for manufacturing the same
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Application No.: US15908921Application Date: 2018-03-01
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Publication No.: US10312257B2Publication Date: 2019-06-04
- Inventor: Akio Kaneko
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JP2016-176672 20160909
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L21/02 ; H01L21/225 ; H01L21/28 ; H01L21/311 ; H01L21/3205 ; H01L21/3213 ; H01L21/324 ; H01L27/11556

Abstract:
A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and second layers on the first semiconductor layer, forming a hole from an upper surface of the stacked body to the first semiconductor layer to expose the first semiconductor layer therein. A first insulating layer is formed on the inner wall of the hole, and a second semiconductor layer is formed on the first insulating layer within the hole, wherein the second semiconductor layer is electrically connected to the first semiconductor layer. A metal layer is provided in contact with at least one of the first and second semiconductor layers. The stacked body, semiconductor layers, insulating layer and metal layer are exposed to an annealing temperature sufficient to cause migration of metal in the metal layer into one of the first and second semiconductor layers.
Public/Granted literature
- US20180190669A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2018-07-05
Information query
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