Invention Grant
- Patent Title: Parallel bit interleaver
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Application No.: US16122466Application Date: 2018-09-05
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Publication No.: US10312942B2Publication Date: 2019-06-04
- Inventor: Mihail Petrov
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: PANASONIC CORPORATION
- Current Assignee: PANASONIC CORPORATION
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: EP11004126 20110518
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/27 ; H04L1/00 ; H03M13/11 ; H03M13/35 ; H03M13/29 ; H03M13/25

Abstract:
A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each made up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.
Public/Granted literature
- US20180375533A1 PARALLEL BIT INTERLEAVER Public/Granted day:2018-12-27
Information query
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