Invention Grant
- Patent Title: System and method for controlling the impact of periodic jitter caused by non-ideal phase interpolators
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Application No.: US15707665Application Date: 2017-09-18
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Publication No.: US10313104B2Publication Date: 2019-06-04
- Inventor: Amiad Dvir , Mike Rolfe Ferrara , Vitaly Zborovski , Mario Caresosa , Ryan Hirth , Assaf Naor
- Applicant: Avago Technologies International Sales Pte. Limited
- Applicant Address: SG Singapore
- Assignee: Avago Technologies International Sales Pte. Limited
- Current Assignee: Avago Technologies International Sales Pte. Limited
- Current Assignee Address: SG Singapore
- Agency: Foley & Lardner LLP
- Main IPC: H04L7/033
- IPC: H04L7/033 ; H04L7/00 ; H04L12/26

Abstract:
In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.
Public/Granted literature
- US20190089520A1 SYSTEM AND METHOD FOR CONTROLLING THE IMPACT OF PERIODIC JITTER CAUSED BY NON-IDEAL PHASE INTERPOLATORS Public/Granted day:2019-03-21
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