Various embodiments provide for analyzing impedance states of a set of nodes in a circuit design and providing a set of reasons for those impedance states. The set of reasons can include a reason regarding why a particular node is reported as being in high-impedance (highz) state or in low-impedance (lowz) state, and the reason may be for a specific time point during transient analysis of the circuit design. Some embodiments are implemented within a debugging utility of an electronic design automation (EDA) software system.