Invention Grant
- Patent Title: Efficient techniques for process variation reduction for static timing analysis
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Application No.: US15149249Application Date: 2016-05-09
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Publication No.: US10318696B1Publication Date: 2019-06-11
- Inventor: Alfred Yeung , Subbayyan Venkatesan , Vamsi Srikantam , Manoj Kulkarni , Ojas Dharia
- Applicant: Ampere Computing LLC
- Applicant Address: US CA Santa Clara
- Assignee: AMPERE COMPUTING LLC
- Current Assignee: AMPERE COMPUTING LLC
- Current Assignee Address: US CA Santa Clara
- Agency: Alston & Bird LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Techniques efficiently improve circuit design to reduce its sensitivity to random device variation. A characterizer component can identify a subset of cells for an integrated circuit that can be representative of respective other cells of a set of cells. The characterizer component can analyze the representative cells of the subset to generate a variation profile, and can map the representative cells to physical cells used in the design of the circuit. A cell library comprising cells that are usable, have limited usage, and/or have general usage can be generated based on analysis results from the mapped cells. The circuit can be reconstructed based on the list of available cells using the cell library. The reconstructed circuit can be analyzed, and in case of a cell(s) violating a constraint, the cell(s) can be modified or enhanced to achieve target performance criteria.
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