Invention Grant
- Patent Title: Semiconductor interconnect structure having a graphene barrier layer
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Application No.: US15675498Application Date: 2017-08-11
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Publication No.: US10319632B2Publication Date: 2019-06-11
- Inventor: Shin-Yi Yang , Ming-Han Lee , Shau-Lin Shue
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532

Abstract:
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.
Public/Granted literature
- US20180166333A1 SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A GRAPHENE BARRIER LAYER Public/Granted day:2018-06-14
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