Invention Grant
- Patent Title: Self-aligned gate edge and local interconnect and method to fabricate same
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Application No.: US15789315Application Date: 2017-10-20
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Publication No.: US10319812B2Publication Date: 2019-06-11
- Inventor: Milton Clair Webb , Mark Bohr , Tahir Ghani , Szuya S. Liao
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/66 ; H01L29/78 ; H01L21/768 ; H01L21/8238 ; H01L23/535 ; H01L27/092 ; H01L29/417

Abstract:
Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
Public/Granted literature
- US20180047808A1 SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME Public/Granted day:2018-02-15
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