Invention Grant
- Patent Title: Vertical DMOS transistor
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Application No.: US16017686Application Date: 2018-06-25
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Publication No.: US10319848B2Publication Date: 2019-06-11
- Inventor: Hideaki Tsuchiko
- Applicant: Alpha and Omega Semiconductor Incorporated
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee: Alpha and Omega Semiconductor Incorporated
- Current Assignee Address: US CA Sunnyvale
- Agency: Innovation Counsel LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/40 ; H01L29/417 ; H01L29/66 ; H01L29/08 ; H01L21/8234 ; H01L27/088 ; H01L21/265 ; H01L21/306 ; H01L27/092 ; H01L29/06
Abstract:
A transistor includes a semiconductor body; a first gate electrode formed on a first portion of the semiconductor body and a second gate electrode formed on a second portion of the semiconductor body. A drain region is formed on a first side of the first gate electrode and a first source region is formed on a second side of the first gate electrode. The drain region is formed on a first side of the second gate electrode and a second source region is formed on a second side of the second gate electrode. A trench is formed in the semiconductor body and positioned in the drain region. A doped sidewall region is formed in the semiconductor body along the sidewall of the trench outside of the trench. The doped sidewall region is in electrical contact with the drain region and forms a vertical drain current path for the transistor.
Public/Granted literature
- US20180308969A1 VERTICAL DMOS TRANSISTOR Public/Granted day:2018-10-25
Information query
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