Invention Grant
- Patent Title: Process for fabricating resistive memory cells
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Application No.: US15352985Application Date: 2016-11-16
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Publication No.: US10319906B2Publication Date: 2019-06-11
- Inventor: Philippe Boivin
- Applicant: STMICROELECTRONICS (ROUSSET) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Seed Intellectual Property Law Group LLP
- Priority: FR1653940 20160502
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L45/00

Abstract:
A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.
Public/Granted literature
- US20170317279A1 PROCESS FOR FABRICATING RESISTIVE MEMORY CELLS Public/Granted day:2017-11-02
Information query
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