Invention Grant
- Patent Title: Fine resolution high speed linear delay element
-
Application No.: US15489221Application Date: 2017-04-17
-
Publication No.: US10320374B2Publication Date: 2019-06-11
- Inventor: Mahdi Parvizi , Sadok Aouini , Naim Ben-Hamida
- Applicant: Ciena Corporation
- Applicant Address: US MD Hanover
- Assignee: Ciena Corporation
- Current Assignee: Ciena Corporation
- Current Assignee Address: US MD Hanover
- Agency: Clements Bernard Walker PLLC
- Agent Christopher L. Bernard; Lawrence A. Baratta, Jr.
- Main IPC: H03K5/13
- IPC: H03K5/13 ; H03K5/134 ; H03K5/00

Abstract:
A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.
Public/Granted literature
- US20180302070A1 FINE RESOLUTION HIGH SPEED LINEAR DELAY ELEMENT Public/Granted day:2018-10-18
Information query
IPC分类: