Invention Grant
- Patent Title: Reduced VSWR switching
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Application No.: US14671785Application Date: 2015-03-27
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Publication No.: US10320381B2Publication Date: 2019-06-11
- Inventor: Kathiravan Krishnamurthi , Jean-Marc Mourant , Olivier Hubert , Shawn Bawell
- Applicant: Kathiravan Krishnamurthi , Jean-Marc Mourant , Olivier Hubert , Shawn Bawell
- Applicant Address: US CA San Jose
- Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Agent Tracy Parris
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K17/693

Abstract:
Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.
Public/Granted literature
- US20160285447A1 Reduced VSWR Switching Public/Granted day:2016-09-29
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