Methods and systems for timing analysis and closure during logic synthesis of synchronous digital circuitry are provided, which may be used to prevent timing conflicts in logic designs that may have data transfers between regions with substantial clock skew. In programmable logic devices having hardened circuitry and programmable fabric, data transfers between memory elements in hardened circuitry and programmable fabric may be subject to substantial clock skews and unknown latencies. Embodiments may employ pre-calculated latencies that may be stored in a file and/or a database, and dynamically retrieved during timing synthesis to determine multicycle constraints to mitigate latencies. Embodiments may employ destination multicycle constraints, which use as reference the clock waveforms delayed due to latency.