Invention Grant
- Patent Title: Pattern based estimation of errors in ADC
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Application No.: US15909378Application Date: 2018-03-01
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Publication No.: US10320405B2Publication Date: 2019-06-11
- Inventor: Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Charles A. Brill; Frank D. Cimino
- Priority: IN201641013525 20160419
- Main IPC: H03M1/00
- IPC: H03M1/00 ; H03M1/06 ; H03M1/12 ; H03M1/10 ; H03M1/16 ; H03M1/36

Abstract:
In described examples, an analog to digital converter (ADC) includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
Public/Granted literature
- US20180191362A1 PATTERN BASED ESTIMATION OF ERRORS IN ADC Public/Granted day:2018-07-05
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