Invention Grant
- Patent Title: Method of testing the resistance of a circuit to a side channel analysis of second order or more
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Application No.: US15439571Application Date: 2017-02-22
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Publication No.: US10320555B2Publication Date: 2019-06-11
- Inventor: Hugues Thiebeauld De La Crouee , Antoine Wurcker
- Applicant: ESHARD
- Applicant Address: FR Martillac
- Assignee: ESHARD
- Current Assignee: ESHARD
- Current Assignee Address: FR Martillac
- Agency: Brake Hughes Bellermann LLP
- Priority: FR1651443 20160222; FR1651444 20160222; FR1651445 20160222
- Main IPC: G06F21/00
- IPC: G06F21/00 ; H04L9/00 ; G01R31/317 ; G09C1/00 ; G06F21/72 ; H04L9/32 ; G06F21/75

Abstract:
A test method can include: acquiring a plurality of value sets including measurements or signals corresponding with activity of a circuit when executing a set of cryptographic operations on secret data, for each value set, selecting at least two subsets of values, computing combined values and counting occurrence numbers of values transformed by a first surjective function applied to the combined values, for each operation and each possible value of a part of the secret data, computing a partial operation result, computing cumulative occurrence number sets by adding the occurrence number sets corresponding to the operations of the operation set, which when applied to a same value of the possible values of the part of the secret data, provide a partial operation result having a same transformed value by a second surjective function, and determine the part of the secret data from the cumulative occurrence number sets.
Public/Granted literature
- US20170244548A1 METHOD OF TESTING THE RESISTANCE OF A CIRCUIT TO A SIDE CHANNEL ANALYSIS OF SECOND ORDER OR MORE Public/Granted day:2017-08-24
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