Invention Grant
- Patent Title: Input/output fencing optimization
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Application No.: US14870390Application Date: 2015-09-30
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Publication No.: US10320702B2Publication Date: 2019-06-11
- Inventor: Jai Gahlot , Amol S. Katkar , Udipta Das , Pranav Peshwe
- Applicant: Veritas Technologies LLC
- Applicant Address: US CA Santa Clara
- Assignee: Veritas Technologies, LLC
- Current Assignee: Veritas Technologies, LLC
- Current Assignee Address: US CA Santa Clara
- Agency: Cambell Stephenson LLP
- Main IPC: H04L12/911
- IPC: H04L12/911 ; H04L29/08 ; H04L12/18 ; H04L12/24 ; G06F11/14 ; G06F11/20

Abstract:
Various systems, methods, and processes to optimize input/output (I/O) fencing operations in systems that implement coordination points are presented. A matrix is generated. The matrix includes information indicating the accessibility of one or more coordination points by a node. The method then transmits the matrix to one or more other nodes.
Public/Granted literature
- US20170093746A1 INPUT/OUTPUT FENCING OPTIMIZATION Public/Granted day:2017-03-30
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