A data transfer circuit that can suppress a voltage drop in a start signal without narrowing a process margin. The data transfer circuit includes N stages of register sections that are connected in series. A register section at an nth stage includes: a first transfer gate that transfers an analog signal; a second transfer gate that transfers one clock out of a clock signal, thereby generating an (n+1)th start signal for a register section at an (n+1)th stage; a control signal generation circuit that generates control signals for the first transfer gate and the second transfer gate; and a holding capacitor. The control signal generation circuit includes a third transfer gate that transfers an nth start signal that is input from a register section at an (n−1)th stage, and the third transfer gate is formed as a CMOS logic circuit.