Invention Grant
- Patent Title: Method for preparing a semiconductor pattern having semiconductor structure of different lengths
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Application No.: US16185889Application Date: 2018-11-09
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Publication No.: US10332749B2Publication Date: 2019-06-25
- Inventor: Chiang-Lin Shih , Shing-Yih Shih
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/308 ; H01L29/06 ; H01L21/3213 ; H01L21/311 ; H01L21/784

Abstract:
A method includes forming a plurality of first core features and one frame feature encircling the first core features. The first core features extend along a first direction and are arranged along a second direction perpendicular to the first direction, and each of the first core features is spaced apart from the frame feature by a first gap along the first direction. The method also includes forming a spacer layer filling the first gaps and forming a plurality of individual recesses entirely separated from each other. The method also includes forming a plurality of second core features in the individual recesses, wherein the second core features are entirely separated from each other and are spaced apart from the frame feature by the spacer layer. The method then removes the spacer layer to form a plurality of openings between the first core features, the second core features and the frame feature.
Public/Granted literature
- US20190080920A1 METHOD FOR PREPARING A SEMICONDUCTOR PATTERN HAVING SEMICONDUCTOR STRUCTURE OF DIFFERENT LENGTHS Public/Granted day:2019-03-14
Information query
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