Invention Grant
- Patent Title: Semiconductor structure with strain reduction
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Application No.: US15797302Application Date: 2017-10-30
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Publication No.: US10332805B2Publication Date: 2019-06-25
- Inventor: Thomas Edward Dungan , Jonathan Kwadwo Abrokwah , Forest Dixon , William Snodgrass
- Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: Avago Technologies International Sales Pte. Limited
- Current Assignee: Avago Technologies International Sales Pte. Limited
- Current Assignee Address: SG Singapore
- Main IPC: H01L27/06
- IPC: H01L27/06 ; H01L29/08 ; H01L29/10 ; H01L29/66 ; H01L29/78 ; H01L29/732 ; H01L21/8234 ; H01L21/8249 ; H01L21/02

Abstract:
A transistor module includes a substrate; a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor. The dielectric cushion includes dielectric material that is softer than the metal pillar, for reducing strain on semiconductor junctions when at least one of tensile or compressive stress is exerted on the metal pillar with respect to the substrate. The transistor module may further include at least one buttress formed between the metal layer and the substrate, adjacent to the transistor, for further reducing strain on the semiconductor junctions by providing at least one corresponding alternative stress path that substantially bypasses the transistor.
Public/Granted literature
- US20190131175A1 SEMICONDUCTOR STRUCTURE WITH STRAIN REDUCTION Public/Granted day:2019-05-02
Information query
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